In digital data systems in general, and in computer systems in particular, there is an ever-increasing drive for larger bandwidth and higher performance. These systems are comprised of discreet integrated circuit chips that are interconnected. Data moves through a chip and between chips in response to clock pulses, which are intended to maintain synchronization of the data in parallel paths. At the extremely high data rates in today's systems, variations in the propagation of data over a bus along one path as compared to another path on the bus (i.e. skew) can exceed one clock cycle. U.S. Pat. No. 6,334,163, which is assigned to the assignee of this application and is incorporated herein by reference, discloses a so called Elastic Interface (EI) that can compensate for bus skew greater than one clock cycle without a performance penalty. Nevertheless, packaging technology has not been able scale up to match the performance and bandwidth of the chip and interface technologies. In order to reduce the number I/O terminals on a chip and the number of conductive paths in a bus between chips, the prior art employs a so called Double Data Rate (DDR) technology, in which data is launched onto the bus at both the rising and falling edges of the clock. This allows the same amount of data to be transferred (i.e. bandwidth) with only half the number of bus conductors and half the number of I/O ports, as compared with a system where data is launched only on a rising or falling clock edge.
In the chips that do not have an on chip clock source operating at twice the data rate, the double data rate interface drivers use a two-to-one multiplexer to launch data to the off chip bus, as illustrated in FIG. 1. The prior art two-to-one multiplexer double data rate driver designs have two limitations. Firstly as shown in FIG. 1, the two output ports from a pair of master-slave latches or flip-flops 212 and 214 feed the data to the data input ports of a 2-to-1 multiplexer 216. These two output ports are also known as the even and odd data ports. One of these two signals (here the odd data) needs to be delayed to meet the 2-to-1 multiplexer select setup and hold time requirements. The prior techniques use a delay element 210 that has a fixed delay time. The delay element time delay must be designed to match its delay for the targeted data cycle time. Changes in cycle time may cause setup or hold violations at the 2-to-1 multiplexer resulting in data corruption.
Secondly, because of the data setup time requirement at the input to the two-to-one multiplexer, the two-to-one multiplexer select signals must be delayed to allow for this set up time. The prior art approach to satisfy this two to one multiplexer data input setup time requirement is to delay the select signal to the multiplexer for the worst case with a delay element 220 that has a fixed delay time, which adds more delay than is necessary in most cases. FIG. 2 is a timing diagram that illustrates the signal timing in the prior-art DDR driver design of FIG. 1 and the delay (Delay1) introduced by fixed delay element 210 and the delay (Delay2) introduced by the fixed delay element 220.
Also, in the prior art double data rate driver design, the clock signal m/s operating the latches that drive the odd and even data may have an unbalanced duty cycle. When this occurs, the data on the bus has a non-uniform duty cycle depending on which latch is the source of the data. This in turn, results in a non-uniformity of the duty cycle of the data on the bus depending on which latch is sourcing the data.